1. Field of the Invention
The invention relates to latch design in sequential logic and more particularly to timed interface circuitry between self-reset logic circuits and a latch.
2. Background Art
In high speed CMOS design, it is desirable to use NMOS devices to perform logic and to use PMOS devices as loads to achieve zero standby power. In dynamic MOS logic, the internal node of a logic tree is first precharged to a power supply voltage and then selectively discharged according to the states of the inputs to the logic circuitry. Because the precharge action for all the gates within a chip usually takes place at the same time, precharge surge current tends to be very high. Self-reset dynamic MOS logic solves this problem by asynchronously resetting the various logic trees, thereby distributing the precharge actions for a number of logic trees over time. A dynamic CMOS logic tree will typically have a plurality of inputs and a number of NMOS gates for logically combining the inputs to produce an output. A typical dynamic CMOS self-reset logic circuit, such as circuit 100 shown in FIG. 1, comprises a well known Differential Cascode Voltage Switch (DCVS) logic tree 101 having a plurality of input terminals and internal nodes x and x-bar, as depicted in FIG. 1. In FIG. 1 and other figures depicting MOS circuit elements, the logic gates are assumed to be NFET gates unless designated by P. Those designated by P are PFET gates. The output nodes x and x-bar are precharged by load pull-up circuits 103 and 105, respectively, which are PMOS devices that charge the respective nodes. The nodes remain charged to a high voltage and are selectively discharged through the gates of the logic tree 101 in response to inputs to the logic tree. The internal nodes x, x-bar are both at a high logic value when charged. To ensure that the logic tree of the subsequently connected circuits does not erroneously receive high logic signals, the internal nodes x and x-bar are connected to inverters 107 and 109, respectively, to provide low outputs q and q-bar during the precharge state. A reset circuit 110 is connected to the output terminals q and q-bar through OR gate 112. The output of the OR gate 112 is low when the logic tree is inactive, i.e. when the internal nodes x and x-bar are charged to the positive level and outputs q and q-bar are low. When either of the outputs q and q-bar is switched to a high logic value, the output of OR gate 112, which will be a high going logic signal, is passed through an odd number of serially connected inverters 115 to produce a time delay. The output of the last of the inverters 115 is connected to both of the charging circuits 103 and 105 which again charge the internal nodes x and x-bar. The delay introduced by the inverters 115 is adjusted such that any circuit connected to the terminals q and q-bar will have sufficient time to evaluate the states of those terminals before internal nodes are again charged and the outputs q and q-bar are returned to the quiescent low state.
The self-reset logic circuit 100 may have inputs connected to an input latch and receiving input data from the input latch. Similarly, its outputs q and q-bar may be connected to an output latch for receiving output data. FIG. 2 is a representation of a prior art dual stage shift register latch (SRL) 120. The latch 120 is a CMOS Differential Cascode Voltage Switch (DCVS) implementation. The SRL shown in FIG. 2 has a first stage 121 and a second stage 131. The first stage 121 has a pair of input gates 124 connected to the q and q-bar output terminals of self-reset logic 140. These gates are connected to a control gate 125 which is operated periodically under the control of a clock pulse, C, causing the state of the output q and q-bar of the first stage 121 to be activated in accordance with the states of the outputs q and q-bar of the self-reset logic 140. Three non-overlapping clock pulses and their complements A and A-bar, B and B-bar, and C and C-bar are used. These pulses are generated by well-known clock circuitry not shown in the drawing. A latching circuit 126 is operated via control gate 128, in response to the low value of the C-clock pulse to latch the states of q and q-bar at the output of the first stage 121. The outputs q and q-bar of the first stage 121 are connected to a pair of input gates 135 of the second stage 131. The gates 135 are activated by means of control gate 136 in response to clock pulse B, referred to as the launch clock, to generate appropriate outputs s and s-bar of the second stage 131. The second stage 131 further includes a pair of gates 137 activated by control gate 138 which is, in turn, activated in the absence of the clock pulse B and serves to latch the state of s and s-bar. The outputs s and s-bar are connected to self-reset logic 150. Pull-up circuits 123 and 133 are provided to charge their respective associated logic circuits. Gate 139 inhibits activation of the second stage circuitry until clock pulse C is low. Under test operation, the first stage 121 and second stage 131 are chained electrically through a scan-in port 142 and a scan-out port 143. In normal system mode operations clocks B and C are active, generating pulses in alternate time slots, and clock A is inactive. In the test mode clocks A and B are operative, generating pulses in alternate time slots, and clock C is inactive. A pair of test input gates 127, operated under control of control gate 129, are provided to receive signal from scan-in port 142. Control gate 129 is operated under control of clock A. Gate 130 serves to latch a test signal in latch 126.
A problem with the prior art design in which self-reset logic is connected to a shift register latch, such as latch 120 shown in FIG. 2, is that the clock that strobes data into the latch does not operate in synchronism with the output pulse from the self-reset logic 140 and, hence, may be unable to capture data from the self-reset logic on a timely basis. A possible solution to that problem is to extend the delay in the reset loop of the self-reset logic (FIG. 1). However, that introduces undesirable time delay. A further problem occurs when a self-reset logic circuit, such as circuit 150, is driven by the outputs s and s-bar of the shift register latch 120. The outputs of the shift register latch are essentially steady state levels while the self-reset logic requires pulses as its input. Accordingly, a timing incompatibility has occurred which can cause circuit errors.